Verilog & SystemVerilog simulator with UVM, power-aware simulation, analog bridge, and built-in verification intelligence. Free in beta.
IEEE 1800-2017. Interfaces, packages, structs, generate, always_comb, always_ff.
Phases, sequences, TLM, factory, concurrent run phases, objections. Mixed-mode support.
Power domains, isolation, retention, level shifters, power state tables, X-injection.
Verilog-A bridge for analog co-simulation.
RV32IM instruction set simulator. Arch tests, firmware co-sim, cross-validation.
Portable stimulus for intent-based test generation.
Clock domain crossing checks. Missing synchronizer detection.
8 agents monitoring compile, elaborate, simulate. Diagnostics on failure.
Standard formats. FST compression. GTKWave compatible.
IR → C++ → native .so. Incremental recompile with source caching.
Liberty cells, SDF timing, gate-level netlist simulation.
Diagnostics with --explain, --rules, and +suppress+ filtering.